explain/tinyelf-arm.md
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00000040 61 6c 6c 40 60 00 00 00 60 00 00 00 05 49 52 43 |all@`...`....IRC|
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+```
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+## ARM sizecoding notes
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+
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+* All ARM instructions are 4 bytes wide
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+* There's a "Thumb" mode, with reduced instructions (eg. no free shifts, no 3-operand instructions) where all instructions are 2 bytes wide
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+* Switch to Thumb like this: `add lr, pc, #1; bx lr`
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+* The `mov` opcode doesn't accept arbitrary immediate values, so you sometimes have to spill values to a "constant pool"
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+* Null bytes decode to `andeq r0, r0` in ARM mode, or to `movs r0, r0` in Thumb mode, both are no-ops, unlike in x86 where null bytes cause a segfault.
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+ * Instruction encoding is relatively sane, so you can predict what low-value 32-bit ints will decode to so you can treat them as (almost-)no-ops.
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+* It's a RISC, so you don't have one-byte-instructions, flexible addressing modes or stringops, but there are a few useful parts in ARM:
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+ * `pc`, `sp` etc. behave as regular registers
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+ * You can shift one operand of an instruction by a constant value for free, it doesn't cost any bytes. (ARM mode only) This can also be used to do fixed-point multiplications etc. (eg. `add r0, r0, lsr #1` for `r0*1.5`)
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+ * `ldmia`/`stmia` are great for copying stuff around.
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